A charge pump may output a positive high-voltage or a negative high-voltage that has a larger magnitude than a voltage supplied from a power supply. For example, a charge pump may be used in a back-bias voltage generator of a semiconductor device (e.g. DRAM or other similar semiconductor device). A charge pump may be used in a voltage generator which generates voltages for writing/erasing data in a cell of an EPROM, an EEPROM, a flash memory element, or other similar devices. A charge pump may be used in a DC-DC converter for components that require a voltage higher than a system voltage.
Example FIG. 1 is a circuit diagram illustrating a positive high-voltage charge pump. A positive high voltage charge pump circuit may include a power supply VDD, a diode unit 110, a capacitor unit 120, a clock unit 130, and an output terminal VOUT 140. Power supply VDD may be used as a power supply for generating a positive high voltage.
Diode unit 110 may include diode D11 connected to input power supply VDD in a forward direction. Diodes D12, D13, D14 and D15 may be serially and sequentially connected in a forward direction.
Capacitor unit 120 may include capacitors C11, C12, C13, and C14 arranged in parallel. Capacitors C11, C12, C13, and C14 may each be to the outputs of diodes D11, D12, D13, and D14. A first clock signal CLK1 in clock unit 130 may be connected to capacitors C11 and C13. A second clock signal CLK2 in clock unit 130 may be connected to capacitors C12 and C13. For example, node N11 may be connected to the output of diode D11, the input of diode D12, and one terminal of capacitor C11; the other terminal of capacitor C11 may be connected to first clock signal CLK1. Node N12 may be connected to the output of diode D12, the input of diode D13, and one terminal of capacitor C12; the other terminal of capacitor C12 may be connected to second clock signal CLK2. Node N13 may be connected to the output of diode D13, the input of diode D14, and one terminal of capacitor C13; the other terminal of capacitor C13 may be connected to first clock signal CLK1. Node N14 may be connected to the output of diode D14, the input of diode D15, and one terminal of capacitor C14; the other terminal of capacitor C14 may be connected to second clock signal CLK2. The output terminal VOUT 140 may output a positive high voltage generated by a pump operation.
Example FIG. 2 illustrates a timing chart of first clock signal CLK1 and second clock signal CLK2. First clock signal CLK1 and second clock signal CLK2 may be out of phase by 180°.
For purposes of explanation and simplicity, it is assumed that threshold voltage Vth of the diodes D11, D12, D13, D14, and D15 are the same; however one of ordinary skill in the art would appreciate that the threshold voltages may be different. As illustrated in the clock input diagram of example FIG. 2, VSS (e.g. a ground level voltage) may be input to one terminal of capacitor C11 during time period T1 of CLK1. Voltage VDD may be input into diode D11 and voltage VDD−Vth may be output from diode D11; in other words, the voltage output from diode D11 may be reduced by threshold voltage Vth. Accordingly, the voltage at node N11 may be VDD−Vth. The capacitance charged in capacitor C11 during time period T1 may be Q1=C11×{(VDD−Vth)−VSS}.
As illustrated in the clock input diagram of example FIG. 2, when CLK1 is in time period T2, a voltage of VDD is input into the terminal of capacitor C11 that is connected to CLK1. The capacitance of capacitor C11 may remain constant. Accordingly, node N11 will become 2VDD−Vth during time period T2. During time period T2, VSS (e.g. ground level voltage) may be input into the terminal of capacitor C12 that is connected to CLK2. Diode D12 may output to node N12 a voltage of node N11 minus Vth (i.e. 2VDD−2Vth). Accordingly, the capacitance charged in capacitor C12 may be Q2=C12×{(2VDD−2Vth)−VSS}.
As illustrated in the clock input diagram of example FIG. 2, during time period T3, the voltage of VDD of CLK2 is input into capacitor C12. During time period T3, since the capacitance charged in capacitor C12 may be constant, node N12 may be come VDD (voltage level of CLK2 terminal of capacitor C12) plus 2VDD−2Vth (voltage charge of capacitor C12), which is 3VDD−2Vth. During time period T3, VSS (i.e. ground level voltage) from CLK1 is input into capacitor C13. Accordingly, diode D13 outputs the voltage of 3VDD−3Vth. Accordingly, the capacitance charged in capacitor C13 may be Q3=C13×{(3VDD−3Vth)−VSS}.
When the clocks CLK1, CLK2 are continuously input, output terminal VOUT 140 may output a voltage of 5VDD−5Vth. Therefore, the positive high voltage charge pump can generate a voltage higher than input voltage VDD. Example FIG. 3 is a diagram of the positive high voltage charge pump simulation.
Example FIG. 4 is a circuit diagram illustrating a negative high voltage charge pump. A negative high voltage charge pump circuit may includes a power supply VSS, a diode unit 210, a capacitor unit 220, a clock unit 230, and an output terminal VOUT 240. Power supply VSS may used as the power supply to generate a negative high voltage.
Diode unit 210 may include a diode D21 connected to an input power supply VSS in a reverse direction. Diodes D22, D23, D24 and D25 may be serially and sequentially connected in a reverse direction. Capacitor unit 220 may include capacitors C21, C22, C23, and C24 in parallel with each other. Each of capacitors C21, C22, C23, and C24 may be connected to the inputs of diodes D21, D22, D23, and D24 respectively. First clock signal CLK1 in clock unit 230 may be connected to capacitor C21 and capacitor C23. Second clock signal CLK2 in clock unit 230 may be connected to capacitors C22 and C24. For example, capacitor C21 may have one terminal connected to node N21 and another terminal connected to CLK1. Capacitor C22 may have one terminal connected to node N22 and another terminal connected to CLK2. Capacitor C23 may have one terminal connected to N23 and another terminal connected to CLK1. Capacitor C24 may have one terminal connected to node N24 and another terminal connected to CLK2. An example timing chart of first clock signal CLK1 and second clock signal CLK2 are illustrated in example FIG. 2. First clock signal CLK1 and second clock signal CLK2 may have a phase difference of 180°.
Output terminal VOUT 240 may output a negative high voltage generated by a pump operation. The operation of a negative high voltage charge pump is generally opposite to the operation of a positive high voltage charge pump. For example, the connecting direction of the diodes and the input power supply are opposite. Example FIG. 5 is an example diagram of a negative high voltage charge pump simulation.
If a device requires both a positive charge pump and a negative charge pump, the device should include a charge pump circuit for each function. For example, a device may require a circuit that includes the positive charge pump circuit illustrate in example FIG. 1 and the negative charge pump circuit illustrated in example FIG. 2. Having two different charge pump circuits may cause complications when miniaturizing a system on chip. Separate charge pumps circuits may each require a regulator for regulating a desired voltage level, which may cause complications when miniaturizing a system on a chip.
A positive high voltage charge pump and a negative high voltage charge pump may be used as individual devices. Production flexibility may be limited as each device is specific to either positive charge pumping or negative charge pumping. Development costs may be unnecessarily spent, as each type of charge pump needs to be independently designed and verified.